The present invention relates generally to the use of chalcogenide materials in semiconductor devices, and more particularly relates to a method for forming a chalcogenide memory layer for non-volatile memory integrated circuits and to memory arrays including multi-state materials therein.
Generally, chalcogenides are multi-state materials, that is, materials which may be electrically stimulated to change states, from an amorphous state to a crystalline state, for example, or to exhibit different resistivities while in the crystalline state. Thus, chalcogenide elements may be utilized, for example, as memory cells in a random access memory (RAM) integrated circuit (IC) to store binary data, or data represented in higher-based systems. Such memory cells will typically include a cell accessible, for example, by a potential applied to digit lines, in a manner conventionally utilized in memory devices. Typically, the cell will include the chalcogenide element as a resistive element, and will include an access or isolation device coupled to the chalcogenide element. In one exemplary implementation suitable for use in a RAM, the access device may be a diode.
Many chalcogenide alloys may be contemplated for use with the present invention. For example, alloys of tellurium, antimony and germanium may be particularly desirable, and alloys having from approximately to 55-85 percent tellurium and on the order of 15-25 percent germanium, are contemplated for use in accordance with the present invention. Preferably, the chalcogenide element will be generally homogeneous (although gradiented alloys may be utilized), and will be alloys formed from tellurium, selenium, germanium, antimony, bismuth, lead, strontium, arsenic, sulfur, silicon, phosphorus, oxygen and mixtures or alloys of such elements. The alloys will be selected so as to establish a material capable of assuming multiple, generally stable, states in response to a stimulus. It is contemplated that in most cases, the stimulus will represent an electrical signal, and that the multiple states will be states of differing electrical resistance. U.S. Pat. No. 5,335,219 is believed to be generally illustrative of the existing state of the art relative to chalcogenide materials, and is believed to provide explanations regarding the current theory of function and operation of chalcogenide elements and their use in memory cells. The specification of U.S. Pat. No. 5,335,219 to Ovshinski et al., issued Aug. 2, 1994, is incorporated herein by reference, for all purposes. An exemplary specific chalcogenide alloy suitable for use in the present invention is one consisting of Te.sub.56 Ge.sub.22 Sb.sub.22.
A cell as generally described above can include electrodes which contact the chalcogenide resistive element. At least one of these electrodes may be one of the identified digit lines, or may be an intermediate conductor. Such a cell will also have a chalcogenide "active area", that is, an area of the chalcogenide element which can be programmed to have different resistivity values. The larger the active area, the more current and the more time is necessary to program the memory cell.
In existing devices where chalcogenide materials are used in memory devices, the chalcogenide elements are small and discrete elements, each physically and electrically isolated from each other. Creating a plurality of separate chalcogenide islands has necessitated additional and precise etching and masking steps. Furthermore, it has required prolonged exposure of unprotected chalcogenide during manufacturing.
Chalcogenide materials are very susceptible to damage by most present silicon semiconductor processing techniques. Silicon processing can require temperatures that liquify chalcogenides, thus destroying them as process-worthy materials. However, chalcogenides are compatible with metalization and passivation processes. In part, this is due to the fact that these processes are performed at lower temperatures; typically below 350.degree. C. Additionally, chalcogenide materials are very easily contaminated. Direct contact between silicon and chalcogenide can "poison" both materials, rendering each inoperable. For this reason, isolation barriers, or diffusion barriers, must often be included to prevent undesirable contamination of the chalcogenide material.
Techniques for forming a chalcogenide memory cell have included the establishing of a chalcogenide electrode with an insulation layer thereon. A hole is then formed in the insulation layer, forming an access port. The chalcogenide layer has then been deposited, establishing electrical communication through the hole. Conventional techniques of forming the hole and the insulation layer have included the application of a high current pulse to open a hole having a diameter on the order of 0.1-0.2 microns. Additional attempts have been made to rely upon photolithography to establish an opening through the insulation layer.
Accordingly, the present invention provides new methods for forming a chalcogenide memory array having a continuous chalcogenide layer extending across a plurality of cells. The methods and apparatus of the present invention prevent damage to the chalcogenide layer and provide higher manufacturing efficiency by reducing the number of masking and etching steps. Additionally, chalcogenide cells manufactured in accordance with the present invention may provide a plurality of high-density memory cells with small and discrete active areas.